The present invention relates generally to semiconductor device processing techniques and, more particularly, to a method for integrating liner formation in back end of line (BEOL) processing.
Metallization patterns on integrated circuits may be formed by depositing a dielectric layer, patterning the dielectric layer by photolithography and reactive ion etching (RIE) to form a groove or trench, and depositing a metal layer that fills the trench in the dielectric layer. The metal layer typically not only fills the trenches but also covers the entire semiconductor wafer. Thereafter, the excess metal is removed using either chemical-mechanical polishing (CMP) or an etch back process so that only the metal in the trenches remains.
This technique, also referred to as “damascene” processing in the art, thus forms inlaid conductors in the dielectric layer. Damascene processing (an additive process) avoids the problems associated with metal etching (a subtractive process), such as, for example, the lack of suitable dry-etch plasma chemistries, problems in dimension control, the formation of small gaps that are difficult to fill with the subsequent dielectric layer, and the entrapment of impurities in inter wiring spaces.
As wire widths in integrated circuits continue to shrink, the electrical conductivity of the wiring material becomes increasingly more important. The initial material of choice since the early days of integrated circuit manufacturing (i.e., aluminum) is becoming less attractive than other materials, such as gold, copper, and silver, which are better conductors. In addition to possessing superior electrical conductivity, such materials are more resistant than aluminum to electromigration, a property that increases in importance as wire cross-sectional areas decrease and applied current densities increase. In particular, copper is seen as a particularly attractive replacement for aluminum as copper offers low cost, ease of processing, lower susceptibility to electromigration, and lower resistivity.
On the other hand, copper has several disadvantages compared to aluminum. For example, copper can diffuse rapidly into and through silicon substrates and dielectric films, such as silicon dioxide. In turn, diffusion of copper into an adjacent dielectric region can cause formation of a conductive path between two interconnect lines, thereby producing an electrical short. Furthermore, diffusion into an adjacent silicon substrate can cause junction leakage, even destroying the device. Copper is easily oxidized during subsequent processing steps, but, unlike aluminum, does not have a hard, stable, self-limited native oxide. Copper also has poor adhesion to capping dielectric layers. Accordingly, the successful replacement of aluminum with copper as an interconnect material requires that such problems be overcome.
In this regard, cap (top surface) liners (e.g., tantalum, titanium based) can be used in combination with trench bottom and sidewall liners in order to encapsulate the copper fill and prevent diffusion of the copper into the surrounding dielectric material in the BEOL areas of the device. Conventionally, such cap liners are formed post-CMP, such as by implementing a selective process to apply the liner material to the top of the copper lines after polishing. Alternatively, cap liners may be formed by blanket deposition of the liner material, followed by selective recession over the insulating layer underneath. In either case, there is the potential for hard shorts within the wiring layers due to the presence of residual liner metal in unwanted regions of the device. Accordingly, it would be desirable to be able to form the cap liner material in a more integrated manner with respect to the damascene process itself, so as to avoid the need for cap liner formation following initial planarization of the wiring metal.